Design  & Analysis of Single Bit Cache Memory Architecture

Dr. Dr Shailendra Dwivedi; Dr. Anurag Shrivastava

doi:https://doi.org/10.51976/jfsa.622307

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Design & Analysis of Single Bit Cache Memory Architecture

Dr Shailendra Dwivedi, Anurag Shrivastava

Vol 6 , Issue 2 , July - December 2023 | Pages: 42-47 | Research Paper

https://doi.org/10.51976/jfsa.622307

Published Online: January 15, 2024

Author Details ( * ) denotes Corresponding author

1. * Dr Shailendra Dwivedi, Professor, Department of Mechanical Engineering, LNCT University, Bhopal, Bhopal, Madhya Pradesh, India (shailendrakdwivedi@gmail.com)

2. Anurag Shrivastava, Assistant Professor, Department of Mechanical Engineering, SR Institute of Management and Technology, Lucknow, Uttar Pradesh, India (onuda@rediffmail.com)

Today's computer environment places a high value on energy efficiency, making cache memory design and optimization crucial. Cache memory is designed to decrease data access latency and enhance system performance by acting as a high-speed buffer between the processor and main memory. Traditional cache designs, on the other hand, can have large power consumption, which is undesirable in systems with tight power limits or in devices that run on batteries. This work investigates six-transistor static RAM cells with voltage latch sensing amplifiers. The cache memory design for the single-bit architecture has been studied at different resistance values. The stability of the design was assessed using Monte Carlo simulation and Process Corner simulation. As the resistance value increases, a single-bit static random access memory cell latch sensing amplifier architecture consumes less energy.

Keywords

Voltage latch sense amplifier (VLSA), write driver circuit (WDC), latchsense amplifier (LSA), six transistorsstatic random-access memory (STSRAM),

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